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TDA9105A
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
PRODUCT PREVIEW
VERTICAL VERTICAL RAMP GENERATOR 50 TO 185Hz AGC LOOP DCCONTROLLEDV-AMP ,V-POS,S-AMP& C-COR ON/OFF SWITCH EWPCC VERTICAL PARABOLA GENERATOR WITH DC CONTROLLED KEYSTONE & AMPLITUDE AUTO TRACKING WITH V-POS & V-AMP CORNER CORRECTION WITH DC CONTROLLED AMPLITUDE GEOMETRY WAVE FORM GENERATOR FOR PARALELLOGRAM & SIDE PIN BALANCE CONTROL AUTO TRACKING WITH V-POS & V-AMP DYNAMIC FOCUS VERTICAL PARABOLA OUTPUT FOR VERTICAL DYNAMIC FOCUS AUTO TRACKING WITH V-POS & V-AMP GENERAL ACCEPT POSITIVE OR NEGATIVE HORIZONTAL & VERTICAL SYNC POLARITIES SEPARATE H & V TTL INPUT COMPOSITE BLANKING OUTPUT DESCRIPTION The TDA9105A is a monolithic integrated circuit assembled in a 42 pins shrink dual in line plastic package.
July 1997
. . . . . . . . . . . . . . . . . . . . . . .
HORIZONTAL DUAL PLL CONCEPT 150kHz MAXIMUM FREQUENCY SELF-ADAPTATIVE X-RAY PROTECTION INPUT DC ADJUSTABLE DUTY-CYCLE 1st PLL LOCK /UNLOCK INFORMATION WIDE RANGE DC CONTROLLED H-POSITION ON/OFF SWITCH (FOR PWR MANAGEMENT) TWO H-DRIVE POLARITIES
This IC controls all the functions related to the horizontal and vertical deflection in multimodes or multisync monitors. This IC, combined with TDA9205 (RGB preamp), STV942x(OSD processor), ST727x(micro controller) and TDA817x (vertical booster), allows to realize very simple and high quality multimodes or multisync monitors.
SHRINK42 (Plastic Package) ORDER CODE : TDA9105A
PIN CONNECTIONS
V-FOCUS H-LOCKOUT PLL2C H-DUTY H-FLY H-GND H-REF FC2 FC1 C0 R0 PLL1F H-LOCKCAP PLL1INHIB H-POS XRAY-IN H-SYNC VCC GND H-OUTEM H-OUTCOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 SPINBAL KEYBAL GEOMOUT EWAMP KEYST EWOUT V-FLY VDCIN V-SYNC V-POS VDCOUT V-AMP V-OUT C-CORR VS-AMP V-CAP V-REF V-AGCCAP V-GND CORNER BLK-OUT
9105A-01.EPS
1/31
This is advance information on a new product now in developme ntor undergoing evaluation . Details are subject to ch ange without notice.
TDA9105A
PIN DESCRIPTION
Pin 1 2 3 4 Name V-FOCUS H-LOCKOUT PLL2C H-DUTY Function Vertical Dynamic Focus Output First PLL Lock/Unlock Output Second PLL Loop Filter DC Control of Horizontal Drive Output Pulse Duty-cycle. If this Pin is grounded, the Horizontal and Vertical Outputs are inhibited. By connecting a Capacitor on this Pin a Soft-start function may be realized on H-drive Output. Horizontal Flyback Input (positive polarity) Horizontal Section Ground Horizontal Section Reference Voltage, must be filtered VCO Low Threshold Filtering Capacitor VCO High Threshold Filtering Capacitor Horizontal Oscillator Capacitor Horizontal Oscillator Resistor First PLL Loop Filter First PLL Lock/Unlock Time Constant Capacitor. When Frequency is changing, a Blanking Pulse is generated on Pin 23, the duration of this Pulse is proportionnal to the Capacitor on Pin 13. TTL-Compatible Input for PLL1 Output Current Inhibition DC Control for Horizontal Centering X-RAY protection Input (with internal latch function) TTL compatible Horizontal Sync Input Supply Voltage (12V Typ.) Ground Horizontal Drive Output (emiter of internal transistor) Horizontal Drive Output (open collector of internal transistor) Blanking Output, activated during frequency changes, when X-RAY Input is triggered, when VS is too low, or when Device is in stand-by mode (through H-DUTY Pin 2) and during H-FLY, V-FLY, V-SYNC, VSawth retrace. DC Control of Corner Correction Amplitude Vertical Section Signal Ground Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator Vertical Section Reference Voltage Vertical Sawtooth Generator Capacitor DC Control of Vertical S-Shape Amplitude DC Control of Vertical C-Correction Vertical Ramp Output (with frequency independant amplitude and S-Correction) DC Control of Vertical Amplitude Adjustment Vertical Position Reference Voltage Output DC Control of Vertical Position Adjustment TTL-Compatible Vertical Sync Input Geometric Correction Reference Voltage Input Vertical Flyback Input (positive polarity) East /West Pincushion Correction Parabola Output DC Control of Keystone Correction DC Control East/West Pincushion Correction Amplitude Side Pin Balance & Parallelogram Correction Parabola Output DC Control of Parallelogram Correction DC Control of Side Pin Correction Amplitude
5 6 7 8 9 10 11 12 13
H-FLY H-GND H-REF FC2 FC1 C0 R0 PLL1F H-LOCKCAP
14 15 16 17 18 19 20 21 22
PLL1INHIB H-POS XRAY-IN H-SYNC VCC GND H-OUTEM H-OUTCOL BLK OUT
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
CORNER V-GND V-AGCCAP V-REF V-CAP VS-AMP C-CORR V-OUT V-AMP VDCOUT V-POS V-SYNC VDCIN V-FLY EWOUT KEYST EWAMP GEOMOUT KEYBAL SPINBAL
2/31
9105A-01.TBL
BLOCK DIAGRAM
H-POS
PLL1F
C0
R0
FC2
FC1
H-FLY
PLL2C
H-LOCKOUT XRAY-IN
H-DUTY
H-OUTCOL
21 20
15
12
10
11
8
9
5
3
2
16
4
H-REF 7 VCO PHASE COMP PHASE SHIFTER PULSE SHAPER H OUTPUT BUFFER
H-OUTEM
19 GND 18 VCC 23 CORNER
V-REF
H-GND 6
PHASE FREQUENCY COMP
H-SYNC 17 VS
PULSE SHAPER POL DETECT LOCK UNLOCK IDENT VIDEO UNLOCK SAFETY PROCESSOR X2
1
V-FOCUS
38 KEYST
PLL1INHIB 14
PLL1 INHIB
H-LOCKCAP 13 X2
37 EWOUT
V-REF 26 V-REF V-MID
39 EWAMP 41 KEYBAL
V-GND 24 VERT OSC RAMP GENERATOR H-FLY V-SYNC
V-SYNC 34
PULSE SHAPER POL DETECT
S CORR
BLK GEN
40 GEOMOUT
TDA9105A
29 27 25 31 30 33
42 SPINBAL 32 36 22 35
28
VCAP
V-OUT
V-POS
V-FLY
VS-AMP
C-CORR
V-AMP
VDCOUT
VAGCCAP
BLK-OUT
VDCIN
TDA9105A
3/31
9105A-02.EPS
TDA9105A
QUICK REFERENCE DATA
Parameter Horizontal Frequency Autosynch Frequency (for Given R0, C0) Hor Sync Polarity Input Compatibility with Composite Sync on H-SYNC Input Lock/Unlock Identification on 1st PLL DC Control for H-Position X-RAY Protection Hor DUTY Adjust Stand-by Function Two Polarities H-Drive Outputs Supply Voltage Monitoring PLL1 Inhibition Input Composite Blanking Output Horizontal Moire Output Vertical Frequency Vertical Autosync (for 150nF) Vertical S-Correction Vertical C-Correction Vertical Amplitude Adjustment Vertical Position Adjustment East/West Parabola Output PCC (Pin Cushion Correction) Amplitude Adjustment Keystone Adjustment Corner Correction Adjustment Dynamic Horizontal Phase Control Output Side Pin Balance Amplitude Adjustment Parallelogram Adjustment Tracking of Geometric Corrections with V-AMP and V-POS Reference Voltage Mode Detection Vertical Dynamic Focus
Notes : 1. Provided PLL inhibition input is used, see application diagram on page 27. 2. One for Horizontal section and one for Vertical section.
4/31
9105A-02.TBL
Value 15 to 150 1 to 3.7 YES YES (see note 1) YES YES YES YES YES YES YES YES YES NO 35 to 200 50 to 185 YES YES YES YES YES YES YES YES YES YES YES YES YES (see note 2) NO YES
Unit kHz FH
Hz Hz
TDA9105A
ABSOLUTE MAXIMUM RATINGS
Symbol V CC V IN Supply Voltage (Pin 18) Max Voltage on Pins 4, 15, 28, 29, 31, 33, 38, 39, 41, 42 Pin 5 Pins 17, 34 Pin 16, 2, 22 Pin 14 ESD Succeptibility Human Body Model, 100pF Discharge through 1.5k EIAJ Norm, 200pF Discharge through 0 Storage Temperature Max Operating Junction Temperature Operating Temperature Parameter Value 13.5 8 1.8 6 12 5 2 300 -40, +150 150 0, +70 Unit V V V V V V kV V C C
9105A-03.TBL 9105A-05.TBL 9105A-04.TBL
VESD
Tstg Tj Toper
C
THERMAL DATA
Symbol Rth (j-a) Parameter Junction-Ambient Thermal Resistance Max. Value 65 Unit C/W
HORIZONTAL SECTION Operating Conditions
Symbol VCO R0min C0min Fmax HsVR Oscillator Resistor Min Value (Pin 11) Oscillator Capacitor Min Value (Pin 10) Maximum Oscillator Frequency Horizontal Sync Input Voltage (Pin 17) 0 6 390 150 5.5 k pF kHz V S 25 % Parameter Test Conditions Min. Typ. Max. Unit
INPUT SECTION MinD Mduty Minimum Input Pulses Duration (Pin 17) Maximum Input Signal Duty Cycle (Pin 17) 0.7
OUTPUT SECTION I5m HOI1 HOI2 Maximum Input Peak Current (Pin 5) Horizontal Drive Output Max Current Pin 20 Pin 21 Sourced current Sink current 5 20 20 mA mA mA
DC CONTROL VOLTAGES DCadj DC Voltage on DC Controls (Pins 4-15) VREF-H = 8V 2 6 V
5/31
TDA9105A
HORIZONTAL SECTION (continued) Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol Parameter Test Conditions Min. Typ. Max. Unit SUPPLY AND REFERENCE VOLTAGES VCC ICC VREF-H IREF-H VREF-V IREF-V Supply Voltage (Pin 18) Supply Current (Pin 18) Reference Voltage for Horizontal Section (Pin 7) Max Sourced Current on V REF-H (Pin 7) Reference Voltage for Vertical Section (Pin 26) Max Sourced Current on V REF-V (Pin 26) I = 2mA 7.4 8 See Figure 1 I = 2mA 7.4 10.8 12 45 8 13.2 65 8.6 5 8.6 5 V mA V mA V mA
INPUT SECTION/PLL1 VINTH VVCO VCOG Hph f0 CR Horizontal Input Threshold Voltage (Pin 17) VCO Control Voltage (Pin 12) VCO Gain, dF/dV (Pin 12) Horizontal Phase Adjust (Pin 15) PLL1 Capture Range Fh Min Fh Max PLLinh IHLock0 VHLock0 PLL 1 Inhibition (Pin 14) (Typ. Threshold = 1.6V) PLL ON PLL OFF V14 V14 I2 V2 with I2 = 10mA 0.25 2 10 0.5 Low level voltage High level voltage VREF-H = 8V R0 = 6.49k, C0 = 680pF % of Horizontal period 25 R0 = 6.49k, C0 = 680pF See conditions on Fig. 1 f0 3.7 x f0 0.8 kHz kHz V V mA V 0.8 2 1.6 to 6.2 17 12.5 27 29 V kHz/V % kHz V
Free Running Frequency (adjustable by changing R0) R0 = 6.49k, C0 = 680pF
Max Output Current on HLock Output Low Level Voltage on HLock Output
SECOND PLL AND HORIZONTAL OUTPUT SECTION FBth Hjit Flyback Input Threshold Voltage (Pin 5) Horizontal Jitter Horizontal Drive Output Duty-cycle (Pin 20 or 21) (see Note) Minimum Maximum Horizontal Drive Low Level Output Voltage See Figure 14 See Application Diagram (Pins 8-9) 0.60 0.70 80 V ppm
HDmin HDmax HDvd HDem
V4 = 2V V4 = 6V V4 = VREF - 500mV Pin 20 to GND, V21-V20 , IOUT = 20mA
31 54.5
33.2 57 61.5 1.1
35.5 59.5 1.7
% % % V V
Horizontal Drive High Level Output Voltage Pin 21 to VCC, (output on Pin 20) IOUT = 20mA Maximum Output Current on Composite Blanking I22 Output Low-Level Voltage on Composite Blanking Output V22 with I22 = 10mA (Blanking ON) Internal Clamping Voltage on 2nd PLL Loop Filter Vmin Output (Pin 3) Vmax Threshold Voltage to Stop H-out, V-out and to V4 activate BLKout (OFF mode when V4 < VOFF) (Pin 4) Supply Voltage to Stop H-out, V-out when VCC < VSCinh (Pin 18)
9.5 TBD
10 8 TBD 10 0.25 1.6 4.0 1 0.5
XRAYth X-RAY Protection Input Threshold Voltage (Pin 16) ISblkO VSblkO Vphi2 VOFF
V mA V V V V
9105A-06.TBL
VSCinh
TBD
7.5
V
Note : If H-drive is taken on Pin 20 (Pin 21 connected to supply), H-D is the ratio of low level duration t o horizontal period. If H-drive is taken on Pin 21 (Pin 20 grounded), H-D is the ratio of high level duration to horizontal period. In both cases, H-D period driving horizontal scanning transistor off.
6/31
TDA9105A
VERTICAL SECTION Operating Conditions
Symbol VSVR VEWM VDHPCM VDHPCm VDFm Rload Parameter Vertical Sync Input Voltage (Pin 34) Maximum EW Output Voltage (Pin 37) Maximum Dynamic Horizontal Phase Control Output Voltage (Pin 40) Minimum Dynamic Horizontal Phase Control Output Voltage (Pin 40) Minimum Vertical Dynamic Focus Output Voltage (Pin 1) Minimum Load for less than 1% Vertical Amplitude Drift (Pin 25) Min. 0 Typ. Max. 5.5 6.5 6.5 Unit V V V V V M
Electrical Characteristics (VCC = 12V, Tamb = 25C)
Symbol IBIASP IBIASN VSth VSBI VRB VRT VRTF VSW VSmDut VSTD VFRF Parameter Test Conditions Min. Typ. 2 0.5 2 0.8 1 2/8 5/8 VRT-0.1 5 15 With 150nF cap V28 = 2V, V29 grounded, Measured on Pin 27 Cosc (Pin27) = 150nF With C27 = 150nF V31 = 6V, C27 = 150nF 50Hz < f < 185Hz V28, V29 grounded V33 = 2V V33 = 4V V33 = 6V 50 100 0.5 3.2 3.5 3.8 2 V31 = 2V V31 = 4V V31 = 6V See Note 2 2 3 4 7/16 5 V/V30pp at T/4 V/V30pp at 3T/4 V29 = 2V V29 = 4V V29 = 6V See Note 1 For V35 = V32 TBD -4 +4 -1.6 0 1.6 TBD TBD 2.2 3.3 70 100 Max. Unit A A V V A VREF-V VREF-V V S % S Hz BiasCurrent (currentsourced by PNPBase)(Pin28) For V28 = 2V Bias Current (Pins 29-31) (sinked by NPN base) For V31 = 6V, V 29 = 6V Vertical Sync Input Threshold Voltage (Pin 34) High-level Low-level Vertical Sync Input Bias Current V34 = 0.8V (Current Sourced by PNP Base) Voltage at Ramp Bottom Point (Pin 27) Voltage at Ramp Top Point (with Sync) (Pin 27) Voltage at Ramp Top Point (without Sync) (Pin 27) Minimum Vertical Sync Pulse Width (Pin 34) Vertical Sync Input Maximum Duty-cycle (Pin 34) Vertical Sawtooth Discharge Time Duration (Pin 27) Vertical Free Running Frequency
ASFR RAFD Rlin Vpos
AUTO-SYNC Frequency (see Note 1) Ramp Amplitude Drift Versus Frequency Ramp Linearity on Pin 30 Vertical Position Adjustment Voltage (Pin 32)
185
Hz ppm/Hz % V V V mA V V V VREF-V mA % % % % %
9105A-08.TBL
3.65
IVPOS VOR
Max Current on Vertical Position Control Output (Pin 32) Vertical Output Voltage (Pin 30) (peak-to-peak voltage on Pin 30) DC Voltage on Vertical Output (Pin30) Vertical Output Maximum Current (Pin 30) Max Vertical S-Correction Amplitude V28 = 2V inhibits S-CORR V28 = 6V gives maximum S-CORR Max Vertical C-Correction Amplitude
3.75
VOUTDC V0I dVS
Ccorr
TBD
VFly Th VFly Inh IBIAS DCIN
Vertical Flyback Threshold (Pin 36) Inhibition of Vertical Flyback Input (Pin 36) Bias Current (Pin 35) (sourced by PNP base)
1 TBD VREF- 0.5 2
V V A
Notes : 1. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on Pin 27 and with a constant ramp amplitude. 2. Typically 3.5V for Vertical reference voltage typical value (8V).
7/31
9105A-07.TBL
0.9 0.9 65
TDA9105A
VERTICAL SECTION (continued) East/West Function
Symbol EWDC TDEWDC EW para Parameter DC Output Voltage (see Figure 2) DC Output Voltage Thermal Drift Parabola Amplitude Test conditions V33 = 4V, V35 = V32 , V38 = 4V, V23 = 4V See Note 2 V28 = 2V, V29 grounded, V31 = 6V, V33 = 4V, V35 = V32, V38 = 4V, V23 = 4V V39 = 6V V39 = 2V V28 = 2V, V29 grounded V33 = 4V, V35 = V32 V38 = 4V, V39 = 6V, V23 = 4V V31 = 2V V31 = 4V V31 = 6V V23 V31 V33 V33 = 4V, V28 = 2V, V29 grounded, = 6V, V38 = 4V, V39 = 6V = 2V, V35 = V32 = 6V, V35 = V32 Min. Typ. 2.5 100 Max. Unit V ppm/C
TBD
1.70 0
V V
EWtrack
Parabola Amplitude versus V-AMP Control (tracking between V-AMP and E/W)
0.45 1.0 1.7
V V V
Keytrack
Keystone versus V-POS control (tracking between V-POS and EW) A/B Ratio B/A Ratio Keystone Amplitude Adjustment
0.54 0.54 0 1.3 1.3 V V V
9105A-09.TBL 9105A-10.TBL
KeyAmp
V23 = 4V, V31 = 6V, V39 = 2V V38 = 4V V38 = 2V V38 = 6V
Notes : 1. When Pin 36 > VREF - 0.5V, Vfly input is inhibited and vertical blanking on composite blanking output is replaced by vertical sawtooth discharge time. 2. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization.
Dynamic Horizontal Phase Control Function
Symbol DHPCDC TDDHPCDC SPBpara Parameter DC Ouput Voltage (see Figure 3) DC Output Voltage Thermal Drift Side Pin Balance Parabola Amplitude (see Figure 3) Test Conditions V33 = 4V, V35 = V32 , V41 = 4V See Note V28 = 2V, V29 grounded, V31 = 6V, V33 = 4V, V35 = V32, V41 = 4V V42 = 6V V42 = 2V V28 = 2V, V29 grounded, V33 = 4V, V35 = V32 , V41 = 4V, V42 = 6V V31 = 2V V31 = 4V V31 = 6V V28 = 2V, V29 grounded, V31 = 6V, V33 = 4V, V35 = V32, V42 = 6V V41 = 6V V41 = 2V V28 V31 V33 V33 = 2V, V29 grounded, = 6V, V41 = 4V, V42 = 6V = 2V, V35 = V32 , = 6V, V35 = V32 Min. Typ. 4 100 Max. Unit V ppm/C
TBD
+1.45 - 1.45
TBD
V V
SPBtrack
Side Pin balance Parabola Amplitude versus V-amp Control (tracking between V-amp and SPB )
0.36 0.82 1.45
V V V
ParAdj
Parallelogram Adjustment Capability A/B ratio (see Figure.3) B/A ratio
TBD TBD
0.12 0.12
Partrack
Parallelogram versus V-pos Control (tracking between V-pos and DHPC) A/B ratio B/A ratio
0.53 0.53
8/31
TDA9105A
VERTICAL SECTION (continued) Vertical Dynamic Focus Function
Symbol VDF DC TDVDFDC VDFAMP Parameter DC Output Voltage (see Figure 4) DC Output Voltage Thermal Drift Parabola Amplitude versus V-amp (tracking between V-amp and VDF) (see Figure 4) Test Conditions V33 = 4V, V35 = V32 See Note V28 = 2V, V29 grounded, V33 = 4V, V35 = V32, V31 = 2V V31 = 4V V31 = 6V V28 = 2V, V29 grounded, V31 = 6V, V33 = 2V, V35 = V32, V33 = 6V, V35 = V32 V31 = 4V, V38 = 4V, V39 = 2V V23 = 2V V23 = 4V V23 = 6V V23 = 6V V31 = 2V V31 = 4V V31 = 6V 0.42 0.42 0.54 0.54 0.55 0 0.55 0.2 0.55 1.7 0.64 0.64 VPP VPP VPP
9105A-11.TBL
Min.
Typ. 6 100
Max.
Unit V ppm/C
-0.84 -1.78 -3.14
-0.72 -1.57 -2.85
-0.6 -1.36 -2.56
V V V
VDFKEY
Parabola Assymetry versus V-pos Control (tracking between V-pos and VDF) A/B ratio B/A ratio Corner Amplitude Adjustment
Corner Amplitude
Tracking Corner with V-amp
VPP VPP VPP
Note : These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes characterization on batches comming from corners of our processes and also temperature characterization.
9/31
10nF
4.7F
1.8k
47nF
47nF
22nF
1F
680pF 1%
6.49k 0.1%
10k
1k
2.2F
VCC
9105A-03.EPS
100nF
10/31
VCC VCC
12 2 10 11 8 9 5 3 16 4 21 20
TDA9105A
Figure 1 : Testing Circuit
15
7
2.2F VCO PHASE COMP PHASE SHIFTER PULSE SHAPER H OUTPUT BUFFER
V-REF
6
PHASE FREQUENCY COMP
23 CORNER 19 1
17
PULSE SHAPER POL DETECT LOCK UNLOCK IDENT VIDEO UNLOCK VS SAFETY PROCESSOR
X2
38
10k
14
PLL1 INHIB
37
13
220nF
X
2
10k
39
26
2.2F V-MID H-FLY V-SYNC
V-REF
41
24
34
PULSE SHAPER POL DETECT VERT OSC RAMP GENERATOR
S CORR
BLK GEN
40
10k
42 29 27 25 31 30 33 32 36 22 35 18
TDA9105A
150nF 1% 470nF 1%
28
10k
12V VCC
TDA9105A
Figure 2 : Exampleof VerticalPositionTrackingEffect Figure 3 : Keystone Effect on E/W Output
V38 = 6V
B EWPARA A
9105A-04.EPS 9105A-05.EPS 9105A-09.EPS 9105A-07.EPS
EWDC
V38 = 2V
Figure 4 : Corner Effect on E/W Output
V23 = 6V
Figure 5 : E/W Output with or without Corner
with corner amplitude V23 > 4V without corner
V23 = 2V
Figure 6 :
Dynamic Horizontal Phase Control Output
V42 = 6V V41 = 6V B
9105A-06.EPS
with corner amplitude V23 < 4V
Figure 7 : Vertical Dynamic Focus Function
A VDFDC VDFAMP B
A
SPBPARA V42 = 2V
9105A-08.EPS
DHPCDC
V33 = 2V
11/31
TDA9105A
TYPICAL VERTICAL OUTPUT WAVEFORMS
Function Control Pin Output Pin Control Voltage 2V Specification Picture Image
2V
Vertical Size
31
30 6V
4V
Vertical Position DC Control
33
32
2V 4V 6V
3.2V 3.5V 3.8V
Vertical DC In/Out
35
1 37 40
T hi s t e rm i na l is a Pin controlling the center position of g eo m et r ic co r re c ti on signals. When connected to Pin 32, "Autotracking" occurs.
2V Vertical S Linearity 25 30
V
6V
V PP V = 4% VPP
9105A-13.TBL / 9105A-10.EPS TO 9105A-16.EPS
2V Vertical C Linearity
VPP
V V = 1.6% V PP V
29
30
6V
VPP V = 1.6% V PP
12/31
TDA9105A
TYPICAL GEOMETRY OUTPUT WAVEFORMS
Function Control Pin Output Pin Control Voltage V38 = 4V 2V Trapezoid Control 38 37 6V
1.3V
Specification
Picture Image
1.3V
V39 = 4V 2V 39 37
1.7V 2.5V 0V
Pin Cushion Control
6V
V42 = 4V 2V Parrallelogram Control 41 40 6V
4V 3V 4V 3V
V41 = 4V 2V Side Pin Balance Control 42 40
1.45V 4V 1.45V
6V
1
3V
Corner
23
37
1.7V 2.5V
Note : The specification of Output voltage is indicated on 4VPP vertical sawtooth output condition.The output voltage depends on vertical sawtooth output voltage.
13/31
9105A-14.TBL / 9105A-17.EPS TO 9105A-27.EPS
Vertical Dynamic Focus
6V
TDA9105A OPERATING DESCRIPTION
GENERAL CONSIDERATIONS Power Supply The typical value of the power supply voltage VCC is 12V. Perfect operation is obtained if VCC is maintained in the limits : 10.8V 13.2V. In order to avoid erratic operation of the circuit during the transient phase of VCC switching on, or switching off, the value of VCC is monitored and the outputs of the circuit are inhibited if VCC < 7.6 typically. In order to have a verygood powersupply rejection, the circuit is internally powered by several internal voltage references (The unique typical value of which is 8V). Two of these voltage references are externally accessible, one for the vertical part and one for the horizontal part. These voltage references can be used for the DC control voltages applied on the concerned pins by the way of potentiometers or digital to analog converters (DAC's). Furthermore it is necessaryto filter the a.m. voltage references by the use of external capacitor connected to ground, in order to minimize the noise and consequently the "jitter" on vertical and horizontal output signals. DC Control Adjustments The circuit has 10 adjustment capabilities : 2 for the horizontal part, 2 for the E/W correction, 4 for the vertical part, 2 for the Dynamic Horizontal phase control. The corresponding inputs of the circuit has to be driven with a DC voltage typically comprised between 2 and 6V for a value of the internal voltage reference of 8V. Figure 8 : Example of Practical DC Control Voltage Generation
9105A-30.EPS
In order to have a good tracking with the voltage reference value, it's better to maintain the control voltages between VREF/4 and 3/4 VREF . The input current of the DC control inputs is typically very low (about a few A). Depending on the internal structure of the inputs, it can be positive or negative (sink or source). HORIZONTAL PART Input section The horizontal input is designed to be sensitive to TTL signals typically comprised between 0 and 5V. The typical threshold of this input is 1.6V.This input stage uses an NPN differential stage and the input current is very low. Figure 9 : Input Structure
H-SYNC
1.6V
9105A-29.EPS
Concerning the duty cycle of the input signal, the following signals may be applied to the circuit. Using internal integration, both signals are recognized on conditionthat Z/T 25%. Synchronisation occurs on the leading edge of the internal sync signal. The minimum value of Z is 0.7s. Figure 10
VREF
PWM DAC Output
DC Control Voltage
PLL1 The PLL1 is composed of a phase comparator, an external filter and a Voltage Controlled Oscillator (VCO). The phase comparator is a "phasefrequency"type, designed in CMOS technology. This kind of phase detector avoids locking on false frequencies. It is followed by a "charge pump", composed of 2 current sources sink and source (I = 1mA typ.)
14/31
9105A-28.EPS
TDA9105A OPERATING DESCRIPTION (continued)
Figure 11 : Principle Diagram
H-LOCKCAP 13 H-LOCKOUT 2 PLL1INHIB PLL1F R0 14 12 11 C0 10
LOCKDET High H-SYNC 17 INPUT INTERFACE COMP1 E2 Low H-POS 15 3.2V PHASE ADJUST OSC
9105A-31.EPS
CHARGE PUMP
PLL INHIBITION
VCO
Figure 13 : Details of VCO
I0 2 I0 Loop Filter 12 6.4V RS FLIP FLOP
4 I0 2
11
1.6V
(1.6V < V12 < 6V) R0 C0
10
6.4V 1.6V 0 0.75T T
9105A-33.EPS
15/31
9105A-32.EPS
The dynamic behaviour of the PLL is fixed by an external filter which integrates the current of the charge pump. A "CRC" filter is generally used (see Figure 9). PLL1 is inhibited by applying a high level on Pin 14 (PLLinhib)which is a TTL compatibleinput. The inhibition results from the opening of a switch located between the charge pump and the filter (see Figure 8). The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the capacitor, by a current proportionnal to the current in the resistor. typical thresholds of sawtooth are 1.6V and 6.4V (see Figure 10). The control voltage of the VCO is typically comprised between 1.6V and 6V (see Figure 10). The theoreticalfrequencyrangeof thisVCO isin the ratio 1 3.75, but due to spread and thermal drift of external componentsand the circuit itself, the effec-
tive frequency range has to be smaller (e.g. 30kHz 85kHz). In the absence of synchronisationsignal the control voltageis equal to 1.6V typ.and the VCO oscillates on its lowest frequency (free frequency). The synchro frequencyhasto be alwayshigherthan the free frequencyand a margin has to be taken. As an example for a synchro range from 30kHz to 85kHz, the suggested free frequency is 27kHz. Figure 12
PLL1F
12
TDA9105A OPERATING DESCRIPTION (continued)
The PLL1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparison between the sawtooth of the VCO and an internal DC voltage adjustable between 2.4V and 4V (by Pin 15). So a 45 phase adjustment is possible (see Figure 11). Figure 14 : PLL1 Timing Diagram
H Osc Sawtooth 0.75T 0.25T 6.4V 2.4V9105A-34.EPS
Phase REF1 is obtained by comparison between the sawtooth and a DC voltage adjustable between 2.4V and 4V. The PLL1 ensures the exact coincidence between the signals phase REF and HSYNS. A T/8 phase adjustment is possible.
The two VCO threshold can be filtered by connecting capacitor on Pins 8-9. The TDA9103 also includes a LOCK/UNLOCK identification block which senses in real-time Figure 15 : LOCK/UNLOCK Block Diagram
whether the PLL is locked on theincoming horizontal sync signal or not. The resulting information is available on HLOCKOUT output (Pin 2). The block diagram of the LOCK/UNLOCK function is described in Figure 12. The NOR1 gate is receiving the phase comparator output pulses (which also drive the charge pump). When the PLL is locked, on point A there is a very small negative pulse (100ns) at each horizontal cycle, so after R-C filter, there is a high level on Pin 13 which force HLOCKOUT to high level (provided that HLOCKOUT is pulled up to VCC). When the PLL is unlocked, the 100ns negative pulse on A becomesmuch larger and consequently the average level on Pin 13 will decrease. When it reaches 6.5V, point B goes to low level forcing HLOCKOUT output to "0". The status of Pin 13 is approximately the following : - Near 0V when there is no H-SYNC, - Between 0 and 4V with H-SYNC frequency different from VCO, - Between 4 and 8V when H-SYNC frequency = VCO frequency but not in phase, - Near to 8V when PLL is locked. It is important to notice that Pin 13 is not an output pin and must only be used for filtering purpose (see Figure 12).
2 20k H-Lock CAP 13 6.5V 220nF
HLOCKOUT
16/31
9105A-35.EPS
From Phase Comparator
NOR1
A
B
TDA9105A OPERATING DESCRIPTION (continued)
PLL2 Figure 16 : PLL2 Timing Diagram
H Osc Sawtooth 0.75T 0.25T 6.4V 4V 1.6V
The PLL2 ensures a constant position of the shaped flyback signal in comparison with the sawtooth of the VCO (see Figure 13). The phase comparator of PLL2 is followed by a charge pump with a 0.5mA (typ.) output current. Theflyback input is composedof an NPNtransistor. This input has to be current driven. The maximum recommanded input current is 2mA (see Figures 14 and 15). Figure 17 : Flyback Input Electrical Diagram
400
HFLY 5
Flyback Internally Shaped Flyback H Drive Ts
9105A-36.EPS
Q1 20k
9105A-37.EPS
Duty Cycle
The duty cycle of H-drive is adjustable between 30% and 50%.
GND 0V
Figure 18 : Dual PLL Block Diagram
C Lockdet HLOCKOUT 2 13 LOCKDET
High
PLL1INHIB Filter R0 C0 14 12 11 10
Horizontal 17 Input
INPUT INTERFACE
COMP1
E2 Low
CHARGE PUMP
PLL INHIBITION Horizontal Adjust 15 PHASE ADJUST
VCO
OSC 3.2V
Adjust Rapcyc 4 RAP CYC
VA VB
Cap PHi2 3
High
4V
CHARGE PUMP
Low
COMP2
EN
FLYBACK 5 Flyback
PWM
BUFFER
21 SortCOLL 20 SortEM
17/31
9105A-38.AI
LOGI PWM
TDA9105A OPERATING DESCRIPTION (continued)
Output Section The H-drive signal is transmitted to the output through a shaping block ensuring a duty cycle adjustable from 30% to 50%. In order to ensure a reliable operation of the scanning power part, the output is inhibited in the following circumstances : - VCC too low, - Xray protection activated, - During the horizontal flyback, - Output voluntarily inhibited through Pin 4. The output stage is composed of a Darlington NPN bipolartransistor. Both the collector and the emitter are accessible (see Figure 16). Theoutput Darlington is in off-statewhen the power scanning transistor is also in off-state. The maximum output current is 20mA, and the correspondingvoltagedrop of theoutput darlington is 1.1V typically. It is evident that the power scanning transistor cannot be directly driven by the integrated circuit. An interface has to be designed between the circuit and the power transistor which can be of bipolar or MOS type. Outputs inhibition The application of a voltage lower than 1V (typ.) on Pin 4 (duty cycle adjust) inhibits the horizontal and vertical outputs. This is not memorised. Figure 20 : Safety Functions Block Diagram
VCC Checking VCC REF XRAY Protection XRAY VCC off H-Duty cycle 1V Flyback 0.7V V OUTPUT INHIBITION S R Q H OUTPUT INHIBITION
X-RAY PROTECTION : the activation of the X-ray protectionis obtained by application of a high level on the X-ray input (>8V). Consequences of X-ray protection are : - Inhibition of H drive output, - Activation of composite blanking output. The reset of this protection is obtained by VCC switch off (see Figure 17). Figure 19 : Output stage simplified diagram, showing the two possibilities of connection
21 V CC
20 VCC
H-DRIVE
21
H-DRIVE
20
Inhibition
V-fly Vsync V sawtooth retrace time H-fly
COMPOSITE BLANKING LOGIC BLOCK
9105A-40.EPS
to 2ND PLL
18/31
9105A-39.EPS
TDA9105A OPERATING DESCRIPTION (continued)
Geometric Corrections The principle is represented in Figure 20. Figure 21 : Geometric Corrections Principle
Analog Multiplier X2 Vertical Ramp VDCIN
Vertical Dynamic Focus Output
EW Amp VDCIN
EW Output Keystone
X2
Corner
Sidepin Amp VDCIN
Key Balance
Starting from the vertical ramp, a parabola shaped is generatedfor E/W correction, dynamichorizontal phase control correction, and vertical dynamic Focus correction. The core of the parabola generator is an analog multiplier. The output current of which is equal to : I = k (VRAMP - VDCIN)2. Where VRAMP is the vertical ramp, typically comprised between 2 and 5V, VDCIN is a vertical DC input adjustable in the range 3.2V 3.8V in order to generate a dissymmetric parabola if required (keystone adjustment). In order to keep good screen geometry for any end user preferences adjustment we implemented the possibility to have "geometry tracking". To enable
9105A-41.EPS
Side Pin Balance Output
the "tracking" function, the VDCOUT must be connected to VDCIN. It is possible to inhibit VPOS tracking by applying a fixed DC voltage on the VDCIN Pin. This DC voltage in that case must be taken from the vertical reference and adjusted to 3.5V with an external bridge resistor. Due to large output stages voltage range (E/W, BALANCE, FOCUS), the combination of tracking function with maximum vertical amplitude max. or min. vertical position and maximumgain on the DC control inputs may leads to the output stages saturation. This must be avoided by limiting the output voltage by apropriate DC control voltages. For E/W part and DynamicHorizontal phasecontrol part, a sawtooth shaped differential current in the followingform is generated: I' = k'(VRAMP -VDCIN). Then I and I' are added together and converted into voltage. For E/W part corner purpose, the following current form is generated and added before voltage conversion I" = k" (V RAMP - VDCIN)4. These two parabola are respectively available on Pin 37 and Pin 40 by the way of an emitter follower which has to be biased by an external resistor (10k). They can be DC coupled with external circuitry. EW VOUT = 2.5V + K1' (VRAMP - VDCIN) + K1 (VRAMP - VDCIN)2 + K1" (VRAMP - VDCIN)4 K1 is adjustable by EW amp control (Pin 39) K1' is adjustable by KEYST control (Pin 38) Dyn. Hor. VOUT = 4V + K2' (VRAMP - VDCIN) Phase Control + K2 (VRAMP - VDCIN)2 K2 is adjustable by SPB amp control (Pin 42) K2' is adjustable by KEYBAL control (Pin 41) For vertical dynamic focus part, only a constant amplitude parabola is generated in the form : VOUT = 6V - 0.75 x (VAMP - VDCIN)2. The output connectionis the same as the two other corrections (Pins 37-40). It is important to note that the parasitic parabola during the discharge of the vertical oscillator capacitor is suppressed.
19/31
TDA9105A OPERATING DESCRIPTION (continued)
VERTICAL PART Figure 22 : Vertical Part Block Diagram
CHARGE CURRENT TRANSCONDUCTANCE AMPLIFIER
REF 27 25 DISCH. OSC CAP SAMPLING SAMP. CAP S CORRECTION 28 VS_AMP POLARITY 29 COR_C C CORRECTION Vlow
Sawth. Disch.
V_SYNC 34
SYNCHRO
OSCILLATOR
30 VERT_OUT 31 VERT_AMP
PARABOLA GENERATOR
37 EW_OUT
38 EW_CENT
23 CORNER
39 EW_AMP
40 SPB_OUT
41 SPB_CENT
42 SPB_AMP
1 V_FOCUS
The vertical part generates a fixed amplitude ramp which can be affected by a S and C correction shape. Then, the amplitudeof thisramp is adjusted to drive an external power stage. The internal reference voltage used for the vertical part is available between Pin 26 and Pin 24. It can be used as voltagereference for any DC adjusment
to keep a high accuracy to each adjustment. Its typical value is :
V26 = VREF = 8V.
The charge of the external capacitor on Pin 27 (VCAP) generates a fixed amplitude ramp between the internal voltages, VL (VL = VREF/4) and VH (VH = 5/8 VREF).
20/31
9105A-42.EPS
TDA9105A OPERATING DESCRIPTION (continued)
VERTICAL PART (continued) Function When the synchronisation pulse is not present, an internal current source sets the free running frequency. For an external capacitor, COSC = 150nF, the typical free running frequency is 100Hz. Typical free running frequency can be calculated by :
f0 (Hz) = 1.5 10-5 1 COSC (nF)
A negative or positive TTL level pulse applied on Pin 34 (VSYNC) can synchronise the ramp in the frequencyrange [fmin, fmax]. This frequencyrange depends on the external capacitor connected on Pin 27. A capacitor in the range [150nF, 220nF] is recommanded for application in the following range : 50Hz to 120Hz. Typical maximum and minimum frequency, at 25C and without any correction (S correction or C correction), can be calculated by : fmax = 2.5 f0 and f min = 0.33 f0 If S or C corrections are applied, these values are slighty affected. If an external synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more constant. An internal correction is activated to adjust it in less than half a second: the highest voltage of the ramp on Pin 27 is sampled on the samplingcapacitorconnected on Pin 25 (VAGCCAP) at each clock pulse and a transconductance amplifier generates the charge current of the capacitor. The ramp amplitude becomes again constant. It is recommandedto use a AGC capacitor with low leakage current. A value lower than 100nA is mandatory. Pin 36, Vfly is the vertical flyback input used to generate the composite blanking signal. If Vfly is not used, (VREF - 0.5), at minimum, must be connected to this input. DC Control Adjustments Then, S and C correction shapes can be added to this ramp. This frequency independent S and C corrections are generated internally; their ampli-
tude are DC adjustable on Pin 28 (VSAMP) and Pin 29 (COR-C). S correction is non effective for VSAMP lower than VREF/4 and maximum for VSAMP = 3/4 VREF. C correction is non effective for COR-C grounded and maximum for : COR-C = VREF /4 or COR-C = 3/4 VREF. Endly, the amplitude of this S and C corrected ramp can be adjusted by the voltage applied on Pin 31 (VAMP). The adjusted ramp is available on Pin 30 (VOUT) to drive an external power stage. The gain of this stageis typically30% when voltage applied on Pin 31 is in the range VREF/4 to 3/4 VREF. The DC value of this ramp is kept constant in the frequency range , for any correction applied on it. Its typical value is : VDCOUT = VMID = 7/16 VREF. A DC voltage is available on Pin 32 (VDCOUT). It is driven by the voltage applied on Pin 33 (VPOS) For a voltage control range between VREF/4 and 3/4 VREF, the voltage available on Pin 32 is : VDCOUT = 7/16 VREF 300mV. So, the VDCOUT voltage is correlated with DC value of VOUT. It increases the accuracy when temperature varies. Basic Equations In first approximation,the amplitude of the ramp on Pin 30 (VOUT) is :
VOUT - VMID = (VCAP - VMID) [1 + 0.16 (VAMP - VREF/2)]
with VMID = 7/16 VREF ; typically 3.5V VMID is the middle value of the ramp on Pin 27 VCAP = V27 , ramp with fixed amplitude. On Pin 32 (VDCOUT), the voltage (in volts) is calculated by : VDCOUT =VMID + 0.16 (VPOS - VREF/2). VPOS is the voltage applied on Pin 33. The current available on Pin 27 (when VSAMP = VREF/4) is : IOSC = 3/8 VREF COSC f COSC : capacitor connected on Pin 27 f synchronisation frequency The recommanded capacitor value on Pin 25 (VAGC) is 470nF. Its ensures a good stability of the internal closed loop.
21/31
TDA9105A
INTERNAL SCHEMATICS Figure 23
Href
5
9105A-47.EPS
Figure 27
Pins 1-37-40 1mA max
Figure 28
9105A-43.EPS
V CC
Figure 24
V CC Pins 2-22 10mA max.
9105A-48.EPS 9105A-50.EPS 9105A-49.EPS
N MOS
9105A-44.EPS
7
Figure 29
Figure 25
Href
8
3
9105A-45.EPS
Figure 26
Figure 30
9
4
9105A-46.EPS
P MOS
22/31
TDA9105A
INTERNAL SCHEMATICS (continued) Figure 31 Figure 35
P MOS
10
14
9105A-51.EPS
Figure 32 Figure 36
11
Figure 33
N MOS P MOS P MOS
9105A-56.EPS
9105A-52.EPS
15
Figure 37
12
9105A-53.EPS
Figure 34
9105A-54.EPS
16
13
N MOS
9105A-57.EPS
23/31
9105A-55.EPS
TDA9105A
INTERNAL SCHEMATICS (continued) Figure 38
P MOS
Figure 40
P MOS
N
25
P
17
9105A-60.EPS
N P
9105A-58.EPS
Figure 41
V CC
Figure 39
21
20mA max.
9105A-59.EPS
26
20
Figure 42
V REF
V REF
V CC
V REF
N
27
P
N MOS
24/31
9105A-62.EPS
9105A-61.EPS
TDA9105A
INTERNAL SCHEMATICS (continued) Figure 43
V REF
Figure 47
VCC
32
28
9105A-67.EPS
9105A-63.EPS
Figure 48
VREF
Figure 44
29
33
9105A-64.EPS
V REF
N MOS
VCC
Figure 49
VREF
30
9105A-65.EPS
Figure 46
VREF
Figure 50
31
35
9105A-66.EPS
25/31
9105A-70.EPS
9105A-69.EPS
34
9105A-68.EPS
Figure 45
TDA9105A
INTERNAL SCHEMATICS (continued) Figure 51 Figure 52
VREF
VREF
36
Pins 23 38-39 41-42
9105A-71.EPS
26/31
9105A-72.EPS
P MOS
J1b J2b J3b
1234567 1234
1234
0/5V to 2/6V INTERFACE
HSIZE
PINCSH
SCOR
KEYST VSHIFT
R75
+12V
KEYBAL
HDF SBPAMP
VSIZE
27k
R30 10k
V REF
CCOR
HSHIFT
R10 3.9k
R16 3.9k
R25 3.9k
R1 3.9k
R4 3.9k
R3 10k
R6 10k
R7 3.9k
R9 10k
R12 10k
R13 3.9k R15 10k R20 120k
R74 10k
R73 10k
R11 120k
R2 120k
R5 120k
R8 120k
R14 120k
R19 3.9k R21 10k R23 120k R22 3.9k
R17 120k
R18 10k
R24 10k R26 120k
HREF
APPLICATION DIAGRAMS
+
C35 1F TP13 C39 1F
+
R84 47k
R83 1k 15k
R87 10k R53 IC1 R52 27k C54 1 42 R92 Q3 BC557 2 41 Q4 BC557 15nF
R93 330k
+12V
R94
R27 10k R29 120k
R28 3.9k
HOUT
HFLY
R91 R89
TP12 +12V
1k
R55 270k J24 R57 R59
J25 DYN 1 FOCUS CON1
5.6k 4.7k
C1 22nF 3 4 39 38 37 R81 C37 1F + VREF E/W POWER STAGE 5 6 C38 1F + R51 6.2k 40
1
270k
2.2 1W C44 220pF
E/W
R88 10k
1k
on C45 220pF C29 100nF C30 47F
off
R54 470
R56
39k
Q9 TIP122
+
+
S1
C36 1F
C34 1F
HREF
+
7 C50 8 35 1% 9 34 33 32 31 30 29 28 TP1 C4 16 27 VREF 150nF C27 17 C5 18 25 470nF 19 24 20 2 to 6V 21 22 23 100nF
+
43.2k
36 R82 1% +12V
SW1 C51 47nF C2 10 11 680pF 5% C43 1F + 47nF
33.2k
D5 1N4148 R86 4.7k
D1 1N4004
C13 470F
+
C32 100nF J21 TP11 -12V
1
+ C12 35V 100F R70 12k R85 15k
7 1 2 6 3
R71
J18
10k
R32 6.49k 1%
12 C7 4.7F +
TP14
C52 C42 1F +
TP15 J23 R37 C10 100nF
4 5
HFLY 1
R90 1
C3 10nF
R31 1.8k
13 14 15
T D A 9 1 0 5
C40 1F +
5.6k
IC2 TDA8172
R41
1.5
C15 220nF
R39
V YOKE
1 2 220 1/2W R36 12k
C41 1F +
3
D4
Figure 53 : Demonstration Board of TDA9105, modified for TDA9105A
C6 220nF
R80 2.7k
R33 C48 1nF
1N4148
C11 470pF
-12V
C14 470F VERTICAL DEFLECTION STAGE
+ R38 5.6k
C31 100nF
10k
R40
XRAY IN
1
1/2W
TP2 26 C28 47F
HSYNC
TP3
J2
+12V
J3
1
C8 100F
+
C9 100nF
+12V
R47a 47 3W T1 L1 10H
R47b 33 3W J22
J19 1
TP5
TP4
+ +
C53 1F R35 C20 100F 63V
1 2
HDRIVE 1k
Q10 BC547 Q2 STD5N20 G 5576-00
3 R44 10
BLK
TP6
VSYNC
TP7 Q1 BC557 R45
J5
R46 560
22k
C19 1nF
HORIZONTAL DRIVER STAGE
TDA9105A
27/31
9105A-73.EPS
Pc1 47k
Pc3 47k
Pc4 47k
Pc5 47k
Pc6 47k
Pc7 47k
Pc8 47k
Pc9 47k
Pc10 47k
Pc11 47k
Pc12 47k
Pc13 4.7k
28/31
Q Q +12V +5V Jc4
1
TDA9105A
+12V
Icc1B 14528
Figure 54 : Control Board
Pc2 47k
APPLICATION DIAGRAMS
Cc2 47pF
RC CX T T
Q
Q
Icc1A 14528
R
+12V
RC CXTT
Cc5 100nF
Cc4 10F
Cc1 47pF
Cc4 10F Jc26
1
CON1 VSIZE
VSHIFT HSHIFT HDF KEYBAL
1234
CCOR
SBPAMP PINCSH
KEYST
SCOR HSIZE
1234567
HOUT
HFLY
1234
Jc1
Jc2
Jc3
9105A-74.EPS
TDA9105A
APPLICATION DIAGRAMS Figure 55 : PCB Layout
29/31
9105A-75.TIF
TDA9105A
APPLICATION DIAGRAMS Figure 56 : Components Layout
30/31
9105A-76.EPS
TDA9105A
PACKAGE MECHANICAL DATA 42 PINS - PLASTIC SHRINK DIP
E E1
A1
A2
B
B1
e
L
A
e1 e2
D c E 42 22
.015 0,38 Gage Plane
1
21
SDIP42
e3 e2
Dimensions A A1 A2 B B1 c D E E1 e e1 e2 e3 L
Min. 0.51 3.05 0.38 0.89 0.23 36.58 15.24 12.70
Millimeters Typ.
Max. 5.08 4.57 0.56 1.14 0.38 37.08 16.00 14.48
Min. 0.020 0.120 0.0149 0.035 0.0090 1.440 0.60 0.50
Inches Typ.
Max. 0.200 0.180 0.0220 0.045 0.0150 1.460 0.629 0.570
3.81 0.46 1.02 0.25 36.83 13.72 1.778 15.24
0.150 0.0181 0.040 0.0098 1.450 0.540 0.070 0.60
2.54
3.30
0.10
0.130
Information furni shed is believed to be accurate and reliable. However, SGS-THOMSON Micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise und erany patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I 2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips 2 2 I C Patent. Rights to use these components in a I C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
31/31
SDIP42.TBL
18.54 1.52 3.56
0.730 0.060 0.140
PMSDIP42.EPS

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